TSMC "Wafer on Wafer" tech could double graphics cards power

General discussion
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The Taiwan Semiconductor Manufacturing Company, better known as TSMC, is holding its 24th annual Technology Symposium in Santa Clara right now, and it’s just unveiled a process that could spell a revolution for graphics cards: Wafer-on-Wafer (WoW) technology.

As the name suggests, WoW works by stacking layers vertically rather than placing them horizontally across a board, much like how 3D NAND flash memory is stacked in modern solid-state drives. What this means is more powerful GPUs for Nvidia and AMD without the need to increase their physical size or shrink the fabrication process.

The technology will allow more cores to be crammed into a single package and means each wafer can communicate with each other extremely quickly and with minimal latencies. What’s especially interesting is the way WoW could be used by manufacturers to place two GPUs on a single card and release it as a product refresh, creating what is essentially two GPUs in one without it appearing as a multiple GPU setup to the operating system.

The biggest issue with WoW right now is the wafer yields. As they are bonded together, if just a single wafer is bad then both have to be discarded, even if there’s no problem with the other one. This means the process would need to be used on production nodes with high yield rates, such as TSMC’s 16nm process, in order to be cost efficient. However, the company aims to use WoW with future 7nm and 5nm fabrication processes.

Article in Techspot.

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Wow is definitely right. Wonder what the timeline is for implementation. :beers::heart_eyes::+1::sparkles:

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I suspect such a process would render the final chips veeeery expensive, at least until it is perfected to a point where the wafer yelds have almost marginal error percentage; probabily a couple of years away.

GPU chips are of huge complexity and transistor count in billions, way more complex than 3D Nand.

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January 2018 :joy::joy::joy: sorry

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I doubt this is what TSMC said and assume it is just an interpretation of the journalist. The problem is that while it allows for high speed interconnection it also brings two disadvantages - the yield drops significantly and thermal power dissipation now becomes even harder. Both these factors are what limits current designs in high TDP and large silicon surface applications, as in CPUs and GPUs.

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Hope to provide a cheap price for the user

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seems same concept as HBM for memory, however even though memory is a prime candidate for such tech we don’t have many cards using it and Nvidia’s next gen is rumoured to be DDR6 instead. Not sure if stacked silicon will really become cost effective anytime soon, even at 16nm.

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** just moving this into the General Discussions category from 8k category as not specific to pimax 8k

Eno

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Double? Yep.
Double Power Consumption.